DMOS is the abbreviation of “Double Diffused Metal Oxide Semiconductor”, which can achieve a very high working frequency and a very high operational speed, wherein two dopants of opposite conductivity types are diffused through an identical window to form self-aligned sub-micron channels.
According to DMOS structures, DMOS can be classified into LDMOS (lateral DMOS) and VMOS (vertical DMOS). LDMOS has three electrodes all extending from the upper surface thereof and is suitable to integrate with other elements. In a LDMOS, the source and the body are formed via a self-aligned diffusion; however, the gate layer and the drain are respectively formed via separated diffusion processes so that the input capacitor and the feedback capacitor can be reduced, and the short-channel effect can also be relieved. In a VDMOS, an N− epitaxial layer is grown from an N+ silicon substrate; after flowing through the channels, electrons flow vertically to exit from the substrate; therefore, the drain electrode extends from the bottom of the chip, and there are only the source electrode and the gate electrode on the top surface of the chip; such a structure can promote the integration level but will limit the usage. In comparison with common MOS transistors, the structure of LDMOS has two features: firstly, P-type and N-type dopants are sequentially diffused through an identical window of an oxide layer to form a very short channel; and secondly, a lightly doped N− drift zone is formed between the channel zone and the drain zone with the doping concentration of the N− drift zone less than that of the channel zone. The N− drift zone sustains most of the applied leakage voltage and increases the punchthrough voltage; therefore, LDMOS can combine the advantages of a high punchthrough voltage and a short channel.
DMOS is a double diffused MOS and its channel length is defined by the two dopants of opposite conductivity types diffused from same window which is formed by single mask to get the channel length very well controlled. In general, the gate poly is used as the window. Since the dopant diffusion needs high temperature drive while sub-micron CMOS (Complementary Metal Oxide Semiconductor) can not afford this thermal cycle, it is difficulty to integrated DMOS in sub-micron CMOS process forming a CDMOS process or sub-micron BiCMOS process forming a Bi-CDMOS process.
U.S. Pat. Nos. 5,491,105 and 6,022,778 have patented their method to solve above problem. U.S. Pat. No. 5,491,105 forms the DMOS body and source by implant two dopants with different diffusion rate through same mask window and then high temperature drive them to define the DMOS channel length before the CMOS active layer. U.S. Pat. No. 6,022,778 forms the DMOS body after gate poly layer by large angle implant and low temperature anneal. To mask the high energy large angle implant the polyside gate material must be used.
U.S. Pat. No. 5,491,105 is really a simple and cost effective method, but it is hard to form PDMOS due to diffusion rates of boron and arsenic are difference while phosphorous and boron are almost same. U.S. Pat. No. 6,022,778 is also a very good method, but its cost is relatively high due to the polyside gate and large angle implant equipment.